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i/o type usb 8-bit otp mcu with spi HT82A525R revision: 1.60 date: january 22, 2014
table of contents features ...............................................................................................4 general description ............................................................................4 block diagram .....................................................................................5 pin assignment ...................................................................................6 pin description ....................................................................................7 absolute maximum ratings ...............................................................8 d.c. characteristics ............................................................................9 a.c. characteristics ..........................................................................10 system architecture..........................................................................11 clocking and pipelining .........................................................................................11 program counter...............................................................................12 stack ....................................................................................................................12 arithmetic and logic unit alu ...........................................................................13 program memory...............................................................................13 organisation .........................................................................................................13 special vectors .....................................................................................................14 data memory ram..........................................................................16 indirect addressing register .................................................................................16 accumulator acc ..............................................................................................16 status register status ...................................................................................16 interrupts ..............................................................................................................18 oscillator configuration ...................................................................20 external crystal oscillator hxt .........................................................................21 internal rc oscillator ...........................................................................................21 internal 12khz oscillator wdtosc ...................................................................22 watchdog timer wdt ....................................................................22 power down operation halt .......................................................23 reset...................................................................................................24 timer/event counter .........................................................................27 input/output ports.............................................................................29 low voltage reset lvr..................................................................30 HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 2 january 22, 2014
spi serial interface............................................................................30 spi interface communication ...............................................................................30 spi pin-shared i/o option table ...........................................................................31 spin registers .....................................................................................................31 spin bus enable/disable .....................................................................................32 spin operation .....................................................................................................32 spin configuration options ..................................................................................34 error detection .....................................................................................................34 programming considerations ...............................................................................34 dma function .......................................................................................................37 suspend wake-up or remote wake-up ..............................................................40 usb interface .......................................................................................................41 pulse width modulator .....................................................................47 pwm registers ....................................................................................................47 8+4 pwm mode modulation .................................................................................48 pwm output control ............................................................................................48 pwm programming example ...............................................................................49 com function for lcd......................................................................50 lcd operation .....................................................................................................50 lcd bias control ..................................................................................................51 options...............................................................................................52 application circuits ..........................................................................53 instruction set ...................................................................................54 introduction ..........................................................................................................54 instruction timing .................................................................................................54 moving and transferring data ..............................................................................54 arithmetic operations ...........................................................................................54 logical and rotate operations .............................................................................54 branches and control transfer .............................................................................55 bit operations .......................................................................................................55 table read operations .........................................................................................55 other operations ..................................................................................................55 instruction set summary ......................................................................................56 instruction definition ........................................................................58 package information .........................................................................68 24-pin ssop (150mil) outline dimensions ...........................................................69 saw type 32-pin (5mm 5mm) qfn outline dimensions .....................................70 48-pin lqfp (7mm 7mm) outline dimensions ....................................................71 HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 3 january 22, 2014
features operating voltage: f sys =6mhz: 3.3v~5.5v f sys =12mhz: 4.5v~5.5v two oscillators: external crystal -- hxt (6mhz or 12 mhz) internal rc -- hirc (12mhz) fully integrated internal 12mhz oscillator requires no external components 4k 15 program memory 192 8 data memory ram usb 2.0 full speed compatible single 16-bit programmable timer/event counters with overflow interrupt single 8-bit programmable timer/event counters with overflow interrupt two spi interfaces shared with i/o lines support spi serial dma or 8-bit parallel dma support serial clock for peripheral device software controlled 4-com lines lcd driver with 1 / 2 bias watchdog timer function power down and wake-up functions to reduce power consumption 3-channel 12-bit pwm output shared with three i/o lines up to 42 bidirectional i/o lines up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v 4 endpoints supported (endpoint 0 included) support interrupt, control & bulk transfer total fifo size is 208 bytes (8,8,64,64 2 for ep0~ep3) 6-level subroutine nesting bit manipulation instruction table read instructions 63 powerful instructions all instructions executed in one or two instruction cycles low voltage reset function (2.2v 0.2v) 24-pin ssop, 32-pin qfn, 48-pin lqfp packages general description this HT82A525R is an 8-bit high performance risc microcontroller designed for usb keyboard mouse and fingerprint product applications. the advantages of low power consumption, i/o flexibility, timer functions, oscillator options, multi-channel pulse width modulation function, watchdog timer, dual spi interfaces, spi serial dma or 8-bit parallel dma , power down and wake-up functions, combine to provide the device with a huge range of functional options while still maintaining a high level of cost effectiveness. the device includes a fully integrated system oscillator hirc, which requires no external components. while the dma function opens up application possibilities such as fingerprint data processing, the device is also suited for a range of other applications such as motor driving, industrial control, consumer products, subsystem controllers, etc. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 4 january 22, 2014
block diagram the following block diagram illustrates the main functional blocks. rev. 1.60 5 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi

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pin assignment HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 6 january 22, 2014
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pin description pin name i/o options description pa0/psync/vsync pa1/pwm0 pa2/pwm1 pa3/pwm2 pa4/hsync pa5/pclk pa6~pa7 i/o pull-high (bit option) wake-up (bit option) bidirectional 8-bit input/output port. each individual pin on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. the psync/ vsync is pin shared with pa0 (dependent on psync/vsync option). pa1~pa3 are pin-shared with pwm0~pwm2. hsync is pin shared with pa4 (dependent on hsync option). pclk is pin shared with pa5 (dependent on pclk option). the power supply for the i/o pins is sourced from the vddio pin. pb0/sclk pb1~pb7 i/o pull-high (bit option) cmos/nmos wake-up (nibble option) bidirectional 8-bit input/output port. each nibble on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pb0~pb7 have cmos/ nmos options. sclk is pin shared with pb0 (dependent on sclk option). the power supply for the i/o pins is sourced from the vddio pin. pc0/int pc1/tmr0 pc2/tmr1 pc3 pc4/scs2 pc5/sck2 pc6/sdi2 pc7/sdo2 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. each nibble on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which nibble on the port have pull-high resistors. int , tmr0, tmr1 are pin shared with pc0, pc1, pc2 respectively. scs2 is pin shared with pc4. sck2 is pin shared with pc5. sdi2 is pin shared with pc6. sdo2 is pin shared with pc7. the power supply for the i/o pins is sourced from the vddio pin. pd0/com0/d0 pd1/com1/d1 pd2/com2/d2 pd3/com3/d3 pd4/d4~pd7/d7 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. each nibble on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which nibble on the port have pull-high resistors. pd0~pd3 are pin-shared with com0~com3. the parallel dma data d0~d7 lines are pin shared with pd0~pd7. the power supply for the i/o pins is sourced from the vddio pin. pe0/scs1 pe1/sck1 pe2/sdi1 pe3/sdo1 pe4~pe7 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. each nibble on this port can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which nibble on the port have pull-high resistors. scs1 is pin shared with pe0. sck1 is pin shared with pe1. sdi1 is pin shared with pe2. sdo is pin shared with pe3. the power supply for the i/o pins is sourced from the vddio pin. pf0/osci i/o (pf0) pull-high wake-up bidirectional i/o line. the pin can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if the pin has a pull-high resistor. the power supply for the i/o pins is sourced from the vdd pin. i(osci) external crystal connection rev. 1.60 7 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
pin name i/o options description pf1/osco i/o (pf1) pull-high wake-up bidirectional i/o line. the pin can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if the pin has a pull-high resistor. the power supply for the i/o pins is sourced from the vdd pin. o(osco) external crystal connection res i schmitt trigger reset input, active low vss hirc and digital negative power supply, ground avss analog negative power supply, ground vddio positive power supply, vddio is used for pa, pb, pc, pd, pe, except pf. for 24-pin ssop package, the vddio pin is double bonding to vdd pin. hvdd hirc positive power supply vdd analog and digital positive power supply v33o o 3.3v regulator output, can be disabled by firmware usbdp i/o usb d+ or 3d ps2 data line. usb function is controlled using software control registers. ps2 function is controlled by the selps2 bit in usc register. usbdm i/o usb d- or 3d ps2 clk line. usb function is controlled using software control registers. ps2 function is controlled by the selps2 bit in usc register. absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v storage temperature ................................................................................................. 50 cto125 c input voltage .................................................................................................v ss 0.3v to v dd +0.3v operating temperature................................................................................................ 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum rat - ings may cause substantial damage to the device. functional operation of this device at other condi - tions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 8 january 22, 2014
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =6mhz 3.3 5.5 v f sys =12mhz 4.5 5.5 v v ddio operating voltage for i/o ports 3.3 v dd v i dd1 operating current (6mhz crystal) 5v no load, f sys =6mhz 48ma i dd2 operating current (12mhz crystal and hirc) 5v no load, f sys =12mhz 7.5 16 ma i stb1 standby current 1 5v no load, system halt, usb mode, lvr disable, wdt disable, clr v33o [usc.4], clr pll [usc.5], clr selps2 [usc.6], clr usbcken [ucc.3], set susp2 [ucc.4], set rctrl [ucc.7], set clk_adj [psd.4] 350 a i stb2 standby current 2 5v no load, system halt, ps2 (i/o) mode, lvr disable, wdt disable, clr v33o [usc.4], clr pll [usc.5], set selps2 [usc.6], clr usbcken [ucc.3], set susp2 [ucc.4], clr rctrl [ucc.7], clr clk_adj [psd.4] 10 a v il1 input low voltage for i/o ports 0 0.3v ddio v v ih1 input high voltage for i/o ports 0.7v ddio v ddio v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol1 i/o port sink current for pa, pb, pc, pd, pe v ol =0.1v ddio , v ddio =3.3v 25 ma i ol2 i/o port sink current for pf0, pf1 v ol =0.1v dd ,v dd =5v 25 ma i oh1 i/o port source current for pa, pb, pc, pd, pe v oh =0.9v ddio , v ddio =3.3v 2 5 ma i oh2 i/o port source current for pf0, pf1 5v v oh =0.9v dd 2 5 ma r ph1 pull-high resistance for pa, pb, pc, pd, pe v ddio =3.3v 40 60 80 k
r ph2 pull-high resistance for pf0, pf1 5v 10 30 50 k
v lvr low voltage reset voltage 2.0 2.2 2.4 v rev. 1.60 9 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
symbol parameter test conditions min. typ. max. unit v dd conditions i lcd_bias v ddio /2 bias current for lcd, v ddio =5v 5v lcdc. rsel[1:0]=00 17.5 25.0 32.5 a lcdc. rsel[1:0]=01 35 50 65 a lcdc. rsel[1:0]=10 70 100 130 a lcdc. rsel[1:0]=11 140 200 260 a v com v ddio /2 voltage for lcd com port, v ddio =5v 5v no load 0.475 0.500 0.525 v ddio a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 5v 6000 12000 khz f sys2 system clock (hirc osc) 4.5v~ 5.5v 11640 12000 12360 khz f timer timer i/p frequency (tmr0/tmr1) 5v 0 f sys khz t wdtosc watchdog oscillator period 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up, reset or wake-up from halt 1024 *t sys t int interrupt pulse width 1 s f pclk parallel frequency 5v 2 5 mhz note: *t sys =1/f sys *f t1 =f sys /4 HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 10 january 22, 2014
system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from a crystal oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. rev. 1.60 11 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi / 3 * / 3 * / 3 * & ,
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program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call , that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is selected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 external interrupt 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 usb interrupt 000000010000 serial interface 1 interrupt 000000010100 serial interface 2 interrupt 000000011000 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits s11~s0: stack register bits #11~#0: instruction code address bits @7~@0: pcl bits stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 6 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 12 january 22, 2014
if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases, which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device contains one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applications, which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. organisation the program memory has a capacity of 4k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. rev. 1.60 13 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi , ? , % c - , ? , % c - , / ? , % c - , 3 ? , % c - , 7 " , ' , ? ? . , ' , ?
special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. location 000h location 000h is reserved for program initialization. after a chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event counter 0 interrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00ch. location 010h location 010h is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 010h. location 014h location 014h is reserved for the serial interface 1. when 8 bits data have been received or transmitted successfully from this serial interface 1, the related interrupts are enabled, and the stack is not full, the program begins execution at location 014h. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 14 january 22, 2014 - ,
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location 018h location 018h is reserved for the serial interface 2. when 8 bits data have been received or transmitted successfully from serial interface 2, the related interrupts are enabled, and the stack is not full, the program begins execution at location 018h. table location any location in the program memory can be used as a look-up tables. there are three methods to read the rom data using two table read instructions tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows: the instruction tabrdc [m] (the current page, one page=256 words), where the table location is defined by tblp (07h) in the current page. the configuration option, tbhp, is disabled (de - fault). the instructions tabrdc [m] , where the table location is defined by registers tblp (07h) and tbhp (01fh). the configuration option, tbhp, is enabled. the instruction tabrdl [m] , where the table locations is defined by registers tblp (07h) in the last page (0f00h~0fffh). instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits @7~@0: table pointer bits only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh. the table higher-order byte register (tblh) is read only and cannot be restored. the table pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before accessing the table, the location must be placed in the tblp and tbhp registers(if the configuration option tbhp is disabled, the value in tbhp has no effect). if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine is likely to be changed by the table read instruction used in the isr. as a result errors may occur. in other words, using the table read instruction in the main routine and in the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the requirements. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp register value. otherwise, if the configuration option tbhp is disabled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. rev. 1.60 15 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
data memory ram the data memory (ram) is designed with 256 8 bits, and is divided into two functional groups, namely; special function registers (64 8 bits) and general purpose data memory (192 8 bits) most of which are readable/writeable, although some are read only. the unused space before 40h is reserved for future expanded usage and reading these locations will get 00h . the general purpose data memory, addressed from 40h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0;01h/mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write operation of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly returns the result 00h. while, writing into it, indirectly leads to no operation. the function of data movement between two indirect addressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. accumulator acc the accumulator is closely related to alu operations. it is also mapped to location 05h of the ram and capable of operating with immediate data. the data movement between two data memory locations must pass through the accumulator. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except for the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 16 january 22, 2014
rev. 1.60 17 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi - , # , " 4 4 / 4 3 4 * 4 6 4 7 4 9 4 ; 4 : 4 4 . 4 4 4 4 4 4 4 / 4 3 4 * 4 6 4 7 4 9 4 ; 4 : 4 4 . 4 4 4 4 4 / 4 / 4 / / 4 / 3 4 / * 4 / 6 4 / 7 4 / 9 4 / ; 4 / : 4 / 4 / . 4 / 4 / 4 / 4 / 4 3 4 3 4 3 / 4 3 3 4 3 * 4 3 6 4 3 7 4 3 9 4 3 ; 4 3 : 4 3 4 3 . 4 3 4 @ , # $ $ , # , g g * 4 3 4 4 ( - , # , " < : / , . " # =

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3 . . . / . / + . + % + 4 + . + % + 4 + . / + / % + / 4 % % ram mapping
bit no. label function 0c carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation. c is also affected by a rotate through carry instruction. 1ac auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction. 2z zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero 3ov overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. 4 pdf power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction 5to watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. 6, 7 unused bit, read as 0 status (0ah) register interrupts this device provides external interrupts (int pin interrupt), usb interrupt, serial interface interrupt and internal timer/event counter interrupts. the interrupt control register0 (intc0;0bh) and interrupt control register1 (intc1:1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or intc1 may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. external interrupts can are triggered by a falling edge transition of int ), and the related interrupt request flag (eif; bit4 of the intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active (int pin), a subroutine call at location 04h occurs. the interrupt flag (eif) and emi bits are all cleared to disable other maskable interrupts. the internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (bit 5 of the intc0), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 18 january 22, 2014
the internal timer/event counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (bit 6 of the intc0), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of the intc1) will be set. the access of the corresponding usb fifo from pc the usb suspend signal from the pc the usb resume signal from the pc usb reset signal bit no. label function 0 emi global interrupt control (1: enable; 0: disable) 1 eei external interrupt control (1: enable; 0: disable) 2 et0i timer/event counter 0 interrupt control (1: enable; 0: disable) 3 et1i timer/event counter 1 interrupt control (1: enable; 0: disable) 4 eif external interrupt request flag (1: active; 0: inactive) 5 t0f timer/event counter 0 interrupt request flag (1: active; 0: inactive) 6 t1f timer/event counter 1 interrupt request flag (1: active; 0: inactive) 7 unused bit, read as 0 intc0 (0bh) register bit no. label function 0 eui usb interrupt control (1: enable; 0: disable) 1 es1ii serial interface 1 interrupt control (1: enable; 0: disable) 2 es2ii serial interface 2 interrupt control (1: enable; 0: disable) 3 unused bit, read as 0 4 usbf usb interrupt request flag (1: active; 0: inactive) 5 si1f serial interface 1 interrupt request flag (1: active; 0: inactive) 6 si2f serial interface 2 interrupt request flag (1: active; 0: inactive) 7 unused bit, read as 0 intc1 (1eh) register when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 10h will occur. the interrupt request flag (usbf) and emi bits will be cleared to dis - able other interrupts. when pc host access the fifo of the HT82A525R, the corresponding request bit of usr is set, and a usb interrupt is triggered when the corresponding interrupt is enabled. so user can easily determine which fifo is accessed. when the interrupt has been served, the corresponding bit should be cleared by firmware. when the HT82A525R receives a usb suspend signal from the host pc, the suspend line (bit0 of the usc) of the HT82A525R is set and a usb interrupt is also triggered. also when the HT82A525R receives a resume signal from the host pc, the resume line (bit3 of the usc) of the HT82A525R is set and a usb interrupt is triggered. rev. 1.60 19 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
whenever a usb reset signal is detected, a usb interrupt is triggered. the serial interface interrupt is indicating by the interrupt flag (si1f: bit 5 of intc1 or si2f: bit 6 of intc1), that is caused by received or transferred a complete 8-bit data between HT82A525R and external device. the serial interface interrupt is controlled by setting the serial interface interrupt control bit (es1ii: bit 1 of intc1 or es2ii: bit2 of intc1). after the interrupt is enabled (by setting sben; bit 4 of sbcr1 or sbcr2), and the stack is not full and the sif is set, a subroutine call to location 14h or 18h occurs. during the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the reti instruction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch usb interrupt 4 10h serial interface 1 interrupt 5 14h serial interface 2 interrupt 6 18h it is recommended that a program does not use the call subroutine within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applica- tions. if only one stack is left and enabling the interrupt is not well controlled, the original control se- quence will be damaged once the call operates in the interrupt subroutine. oscillator configuration various oscillator options offer the user a wide range of functions according to their various application requirements. two types of system clocks and an internal 12khz oscillator can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. the two methods of generating the system clock are: external crystal oscillator internal rc oscillator one of these two methods must be selected using the configuration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 20 january 22, 2014
external crystal oscillator hxt the simple connection of a crystal across osci and osco will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. however, for some crystals, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal manufacturer s specification. the external parallel feedback resistor, r p , is normally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, therefore typical values @ 5v, 25 c ca cb rf 11~13pf 13~15pf 800k
oscillator internal component values internal rc oscillator the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fixed oscillation frequency of 12mhz will have a tolerance within 3%. the hirc has an automatic clock adjust function which can be used to adjust the hirc frequency and to minimise the frequency deviation caused by temperature variation. this function is controlled by the clk_adj and clr_rcp bits in the psd register. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pf0 and pf1 are free for use as normal i/o pins. rev. 1.60 21 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi

internal rc oscillator hirc
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bit no. label r/w function 0 ps2_dao r/w usbdm/data pin output control bit 0: output low ; 1: output high this control bit is used to generate the usbdm/data pin output signal in the 3d ps2 mouse mode. the default value is 1 . 1 ps2_cko r/w usbdp/clk pin output control bit 0: output low ; 1: output high this control bit is used to generate the usbdp/clk pin output signal in the 3d ps2 mouse mode. the default value is 1 . 2 undefined bit, read as unknown 3 pu r/w usbdp and usbdm internal 310k
pull-high resistor select bit 0: without pull up resistor; 1: with pull up resistor 4 clk_adj r/w automatic clock adjustment control bit 0: disable (default); 1:enable this bit is used to adjust the hirc mode system clock, to reduce the frequency deviation due to temperature issue. in the power-down mode, this bit should be clear to reduce power consumption. 5 clr_rcp r/w this bit is must enable and then disable by f/w to clear hirc initial parameters after power on. 0: disable (default); 1:enable 6~7 undefined bit, read as 0 psd (3ah) register internal 12khz oscillator wdtosc the low frequency internal 12k rc oscillator (wdtosc) is a free running on-chip rc oscillator, and no external components are required. although when the system enters the halt mode, the system clock stops, the wdt oscillator will still operate if this oscillator is selected. its period is approximately 83.3 s. the wdt oscillator can also be disabled to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdtosc) or the system clock divided by 4 determined by a configuration option. the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by a configuration option. if the watchdog timer is disabled, all executions related to the wdt results in no operation. once the internal wdt oscillator (rc oscillator with a period of 83.3 s , normally at 5v) is selected, it is divided by 2 12 ~2 16 by configuration option to get the wdt time-out period. the wdt time-out minimum period is about 340ms. this time-out period may vary with temperature, vdd and process variations. by selection from the wdt option, longer time-out periods can be realized. if the wdt time-out is selected as 2 15 , the maximum time-out period is divided by 2 15 , about 2.7s. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. if the device operates in a noisy environment, using the on-chip rc oscillator (wdtosc) is strongly recommended, since the halt instruction will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to . whereas in the halt mode, the overflow will initialize a warm reset and only the program counter and stack pointer are reset to zero. to clear the contents of wdt, three methods are adopted; external reset (a HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 22 january 22, 2014
low level to res ), software instructions, or a halt instruction. the software instructions include clr wdt and the other set -- clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the option -- clr wdt times selection option. if the clr wdt is selected (i.e. clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt, otherwise, the wdt may reset the chip due to time-out. there are two timer out wdt clear modes selected by configuration option. one is half wdt clear and the other is full wdt scale .the half wdt clear is only to clear the highest two bits of wdt counter and the full wdt clear is to clear all bits of wdt counter. power down operation halt the halt mode is initialized by the halt instruction and results in the following: the system oscillator is turned off but the wdt oscillator keeps running (if the wdt oscillator is selected). the contents of the on-chip ram and registers remain unchanged. the wdt will be cleared and start recounting (if the wdt clock source is from the wdt oscillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can quit the halt mode in many ways, by an external reset, an interrupt (except serial in - terface interrupt and serial interface 2 interrupt), an external falling edge signal on i/o ports or a wdt overflow. an external reset causes a device initialization and the wdt overflow performs a warm re - set . after examining the to and pdf flags, the cause for a chip reset can be determined. the pdf flag is cleared by a system power-up or by executing the clr wdt instruction and is set when executing the halt instruction. on the other hand, the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; and leaves the others in their original status. the port a wake-up and interrupt methods can be considered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if it awakens from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. but if the interrupt is enabled and the stack is not full, a regular interrupt response takes place. when an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. if a wake-up event occurs, it takes 1024 f sys (system clock period) to resume normal operation. in other words, a dummy period is inserted after wake-up. if the wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one cycle. rev. 1.60 23 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi ' + / ; " # , - ? * c $ + , # - # ? , ' + < / ? 4 f = ' + 4 - ' , + , - 2 , # 4 - ' , + , - , , , , , / , , , 8 / , , , , ' # , , , , , , / , , , 8 / , , , , ' # , , , , , , / , , , 8 / , , , , ' # , , , , , / , , , 8 / , , , , ' # / 3 * 6 3 * 6 7 - - , + , - , , , , , / , , , , ' , , , , , , / , , , , ' , , , , , , / , , , , ' , , , , , / , , , , ' 7 6 * 3 - - , + , - ! @ , ' , i , ' + watchdog timer
however, if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset may occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and stack pointer, leaving the other circuits in their origi - nal state. some registers remain unaffected during any other reset conditions. most registers are re - set to the initial condition when the reset conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up 0 0 res reset during normal operation 0 0 res wake-up at halt 1 u wdt time-out during normal operation 1 1 wdt wake-up at halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the halt state or during power up. awaking from the halt state or system power up, an sst delay is added. an extra sst delay is added during power up period, and any wake-up from halt may enable only the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler, divider cleared wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 24 january 22, 2014
the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u u--- 00-0 1000 00-0 1000 tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 rev. 1.60 25 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi + , # + 4 % - $ # e 2 , 2 d , - + > - 2 # reset configuration 1 , 2 & , , # reset timing chart ? ? 0 j 0 j reset circuit note: * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference.
register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pf ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu ---- --11 ---- --11 pfc ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu ---- --11 ---- --11 intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu usc 1000 x00x uuuu xuux 1000 x00x 1000 x00x uuuu xuux u-00 0100 u-00 0100 usr 0000 0000 0000 uuuu 0000 0000 0000 0000 0000 uuuu 0000 0000 0000 0000 ucc -000 0000 -uuu uuuu -000 0000 -000 0000 -uuu uuuu -uu0 u000 -uu0 u000 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall ---- 1110 ---- uuuu ---- 1110 ---- 1110 ---- uuuu ---- 1110 ---- 1110 sies 0x0x x000 uxux xxuu 0x0x x000 0x0x x000 uxux xxuu 0x0x x000 0x0x x000 misc 0xx- -000 uxx- -uuu 0xx- -000 0xx- -000 uxx- -uuu 000- -000 000- -000 setio ---- 1110 ---- uuuu ---- 1110 ---- 1110 ---- uuuu ---- 1110 ---- 1110 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 sbcr1 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sbcr2 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pwmbr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm0drl 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 pwm0drh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwmbr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm1drl 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 pwm1drh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwmbr2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm2drl 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 pwm2drh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 clk ---00 0000 --uu uuuu ---00 0000 ---00 0000 --uu uuuu --uu uuuu --uu uuuu psd --00 0x11 --uu ux11 --00 0x11 --00 0x11 --uu ux11 --uu ux11 --uu ux11 lcdc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 26 january 22, 2014
timer/event counter two timer/event counters (tmr0, tmr1) are implemented in the microcontroller. the timer/event counter 0 contains a 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys . the timer/event counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. there are five registers related to the timer/event counter 0; tmr0 (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). for 16bits timer to write data to tmr1l will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l registers. the timer/event counter 1 preload register is changed by each writing tmr1h operations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr0c (tmr1c) is the timer/event counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. the t0m0, t0m1 (tmr0c) and t1m0, t1m1 (tmr1c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0, tmr1), and the counting is based on the internal selected clock source. in the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at ffffh (for 16 bits timer is ffffh, bit 8 bits timer will be ffh). once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (t0f; bit 5 of the intc0, t1f; bit 6 of the intc0). in the pulse width measurement mode with the values of the t0on/t1on and t0e/t1e bits equal to 1, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the t0e/t1e bit is 0 ), it will start counting until the tmr0 (tmr1) returns to the original level and resets the t0on/t1on. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on is set. the cycle measurement will re-function as long as it receives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (t0on: bit 4 of the tmr0c; t10n: bit 4 of the tmr1c) should be set to 1. in the pulse width measurement mode, the t0on/t1on is automatically cleared after the measurement cycle is completed. but in the other two modes, the t0on/t1on can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i or et1i disables the related interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. the timer/event counter still continues its operation until an overflow occurs. rev. 1.60 27 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors, as this may results in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr0/tmr1 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1 is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. after this procedure, the timer/event function can be operated normally. bit no. label function 0~2 unused bit, read as 0 3 t0e timer 0 active edge control bit 0: active on low to high 1: active on high to low 4 t0on timer 0 control bit 0: disable 1: enable 5 unused bit, read as 0 6 7 t0m0 t0m1 t0m1, t0m0: timer 0 operating mode control bits 00: unused 01: event counter mode (external clock) 10: timer mode (internal clock) 11: pulse width measurement mode tmr0c (0eh) register bit no. label function 0~2 unused bit, read as 0 3 t1e timer 1 active edge control bit 0: active on low to high 1: active on high to low 4 t1on timer 1 control bit 0: disable 1: enable 5 unused bit, read as 0 6 7 t1m0 t1m1 t1m1, t1m0: timer 1 operating mode control bits 00: unused 01: event counter mode ( external clock) 10: timer mode ( internal clock) 11: pulse width measurement mode tmr1c (11h) register HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 28 january 22, 2014
input/output ports there are 42 bidirectional input/output lines in the microcontroller, labeled from pa to pf, which are mapped to the data memory of [12h], [14h], [16h], [18h], [1ah] and [1ch] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, 18h, 1ah or 1ch). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pec, pfc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must write a 1 . the input source also depends on the control register. if the control register bit is 1 the input will read the pad state. if the control register bit is 0 the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration (except pb can be configured as cmos output or nmos output). these control registers are mapped to locations 13h, 15h, 17h, 19h, 1bh and 1dh. pa0 is pin-shared with psync or vsync signal (dependent on psync/vsync option). pb0 is pin-shared with sclk signal (dependent on sclk option). after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h, 18h , 1ah or 1ch ) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. all the i/o ports have the capability of waking-up the device. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. note that the i/o lines, from pa to pe, the power supply is from vddio pin, except pf, from vdd. rev. 1.60 29 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi , , c , $ , - ! - $ , # c , . # - $ c ' - e ,
; 2 . , c , , , ' ) * timer/event counter 0 c , $ , - 7 2 . - $ , # , . # - $ c ' - e ,
% e , . " . ' ' ! 4 & , . " % e , . " 7 2 d , c , , ' ) * timer/event counter 1
low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage range (0.9v~v lvr ) has to be maintained for over 1ms, otherwise, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform a chip reset. spi serial interface this device includes two spi serial interfaces, namely spi1 and spi2. the spi interface is a full duplex serial data link, originally designed by motorola, which allows multiple devices connected to the same spi bus to communicate with each other. the devices communicate using a master/slave technique where only the single master device can initiate a data transfer. a simple four line signal bus is used for all communication and these pins are shared with normal i/o pins. the spi function is selected and controlled via configuration options and an sbcr register. the following table shows the spi pin-shared options. note that the spin stands for spi1 and spi2. the n , known as 1 or 2 , is used to distinguish these two spis in the following sections. spi interface communication four lines are used for spin communication known as sdin - serial data input, sdon - serial data output, sckn -serial clock and scsn - slave select. note that the condition of the slave select line is conditioned by the csenn bit in the sbcrn control register. if the csenn bit is high then the scsn line is active while if the bit is low then the scsn line will be a normal i/o pin. the following timing diagram depicts the basic timing protocol of the spin bus. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 30 january 22, 2014
, < , ' , 8 =
! , ' , , ' , , ' , / " # , + ? 2 $ , , # k k k - , . - - 2 & & , . # + , - , # & , # $ , - , # + , , # , . ) ! 5 , ) ! + 5 , / + 3 + / 5 , * 4 ) ! 6 % 5 , 7 8 9 . % 5 , . 8 . 9
! 5 , / 5 , 3 * / 5 , 6 / 7
/ 5 , 9 / / / / 3 3 3 * * 8 9 9 5 , /
5 , 3 * 8 9
5 , k # ? , # ? , % % ! . input/output ports
spi pin-shared i/o option table the following table shows how the spin pins are related to the spin configuration options and the control bits in the sbcrn register. configuration options register options pin-shared i/o functions note spi_enn spi_csenn sbenn csenn spin or i/o scsn or i/o 0 x x x i/o i/o 1 0 x x spin i/o scsn not floating 1 1 x 0 spin i/o scsn not floating 1 1 x 1 spin scsn spin registers there are several registers associated with the spin interface. these are the sbcrn register which is the control register and the sbdrn which is the data register. the sbcrn register is used to setup the required setup parameters for the spin bus and also used to store associated operating flags, while the sbdrn register is used for data storage. after power on, the contents of the sbdrn register will be in an unknown condition while the sbcrn register will default to the condition below: rev. 1.60 31 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi 9 7 6 * 3 / . , < c $ , , # = , . ' ' % , . # # , , - c

- , . $ , , - ? - ? , - " / . !
- , . # " , - . ! + , . + % , - $ 5 , # . ! ! ! + , . + , . , d - # d - ! # , , - c ! . ! $ 5 , # $ 5 , # + % @ , # , d " ,
, - $ , d " , # # ! @ , d - $ # d - , & , # - , ' , , , , , , , , , , , , , , , 0 , # , $ @ , , i , e & e & , , , ' , , , , , , , , , , , , , , / 0 , # - c , $ @ , , i , e & e & , , , - , ' . ! @ , d - $ # d - , # - , d # , < @ , - # , - - , # # , ' - # = , , , , , , , , , , , , , , 0 , + & , . ! i 5 , - - , # # , ' - # , # & - $ , d , - # $ , , , , , , , , , , , , , , / 0 , + & , . ! i 5 , - - ,
, - $ , ' , # , # & - $ , # " , , ' - , # , @ , $ , # $ , , c $ 5 , @ , $ , # , # , , # - - , , c $
l % , @ , - ? , - " , # ' - - , $ , @ , ' , ! @ , , i , , spi block diagram
cksn m1n m0n sbenn mlsn csenn wcoln trfn 01100000 note that data written to the sbdrn register will only be written to the txrxn buffer, whereas data read from the sbdrn register will actual be read from the register. spin bus enable/disable to enable the spin bus, csenn = 1, scsn =0, then wait for data to be written to the sbdrn (txrxn buffer) register. for the master mode, after data has been written to the (txrxn buffer) register, then transmission or reception will start automatically. when all the data has been transferred the trfn bit should be set. for the slave mode, when clock pulses are received on sckn, data in the txrxn buffer will be shifted out or data on sdin will be shifted in. to disable the spin bus sckn, sdin, sdon, scsn will enter i/o mode. bit no. label function 0 trfn spin transmit/receive complete flag 0: data is being transferred; 1: spin data transmission is completed the trfn bit is the transmit/receive complete flag and is set 1 automatically when an spin data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. 1 wcoln spin write collision flag 0: no collision; 1: collision the wcoln flag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simdn register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcoln bit can be disabled or enabled via configuration option. 2 csenn spin scs pin control 0: disable; 1: enable the csenn bit is used as an enable/disable for the scsn pin. if this bit is low, then the scsbn pin will be disabled and placed into an i/o mode. if the bit is high the scsbn pin will be enabled and used as a select pin. note that using the csenn bit can be disabled or enabled via configuration option. 3 mlsn spin data shift order 0: lsb; 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. 4 sbenn serial bus control bit 0: disable; 1: enable depend upon csenn bit. 5 6 m1n m0n master/slave/baud rate control bits 00: master, baud rate is f sio 01: master, baud rate is f sio /4 10: master, baud rate is f sio /16 11: slave mode 7 cksn clock source select bit 0: f sio =f sys /4; 1: f sio =f sys note: the trfn flag will also generate an spin interrupt signal, for more information refer to the interrupt section. spin interface control register spin operation HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 32 january 22, 2014
all communication is carried out using the 4-line interface for both master or slave mode which is controlled by configuration options and the sbcrn register. the timing diagram shows the basic operation of the bus. the csenn bit in the sbcrn register and the spin_en configuration option control the overall function of the spin interface. setting these two bits high, will enable the spin interface by allowing the scsn line to be active, which can then be used to control the spin interface. meanwhile, the pe0~pe3 or pc4~pc7 will be the spin function pins and the corresponding pull-high resistor will be disabled by hardware. if the csenn bit is low, the spin interface will be disabled and the scsn pins will be setup as normal i/o pins and can therefore not be used for control of the spin interface. the sbenn bit in the sbcrn register must also be high which will place the sdin line in a floating condition and the sdon line high. if in master mode the sckn line will be either high or low depending upon the clock polarity configuration option. if in slave mode the sckn line will be in a floating condition. if sbenn is low then the bus will be disabled and scsn, sdin, sdon and sckn will all be in a i/o mode. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written to the sbdrn register. in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode step 1 select the clock source using the cksn bit in the sbcrn control register step 2 setup the m0n and m1n bits in the sbcrn control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. step 3 setup the csenn bit and setup the mlsn bit to choose if the data is msb or lsb first, this must be same as the slave device. step 4 setup the sbenn bit in the sbcrn control register to enable the spin interface. step 5 for write operations: write the data to the sbdrn register, which will actually place the data into the txrxn buffer. then use the sckn and scsn lines to output the data. goto to step 6.for read operations: the data transferred in on the sdin line will be stored in the txrxn buffer until all the data has been received at which point it will be latched into the sbdrn register. step 6 check the wcoln bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7 check the trfn bit or wait for an sbin serial bus interrupt. step 8 read data from the register. step 9 clear trfn. step10 goto step 5. slave mode rev. 1.60 33 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
step 1 the cksn bit has a don t care value in the slave mode. step 2 setup the m0n and m1n bits to 11 to select the slave mode. the cksn bit is don t care. step 3 setup the csenn bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the master device. step 4 setup the sbenn bit in the sbcrn control register to enable the spin interface. step 5 for write operations: write data to the sbcrn register, which will actually place the data into the txrxn register, then wait for the master clock and scsn signal. after this goto step 6. for read operations: the data transferred in on the sdin line will be stored in the txrxn buffer until all the data has been received at which point it will be latched into the sbdrn register. step 6 check the wcoln bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7 check the trfn bit or wait for an sbi serial bus interrupt. step 8 read data from the sbdrn register. step 9 clear trfn step10 goto step 5 spin configuration options several configuration options exist for the spin interface function which must be setup during device programming. one option is to enable the operation of the wcoln, write collision bit, in the sbcrn register. another option exists to select the clock polarity of the sckn line. a configuration option also exists to disable or enable the operation of the csenn bit in the sbcrn register. if the configuration option disables the csenn bit then this bit cannot be used to affect overall control of the spin interface. error detection the wcoln bit in the sbcrn register is provided to indicate errors during data transfer. the bit is set by the serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the sbdrn register takes place during a data transfer operation and will prevent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcoln bit can be disabled or enabled by a configuration option. programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trfn bit is used to generate an interrupt when the data has been transferred or received. there are two spin modes for different data output format, selected by a configuration option. the HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 34 january 22, 2014
following diagram illustrates these two data format, which are dependent on the spin_cpol and spin_mode options. rev. 1.60 35 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi . ' - . ' - ! @ , g g , # , ? e 0 . ! % ! + % 9 7 6 * 3 / 9 7 6 * 3 / . @ , - , . # , - , # . @ , - , . # , , # 9 7 6 / * 3 3 * / 6 7 9 9 7 6 / * 3 3 * / 6 7 9
<
l % i = <
l % i = ! " # $ % . ! i ! i , $ , e , $ , , . . ! i 5 , ! i , $ , e , $ , , . , < , , ,
, $ = 9 7 6 / * 3 3 * / 6 7 9 9 7 6 / * 3 3 * / 6 7 9 ! " # $ & . ! i ! i , $ , e , $ , , . . ! i 5 , ! i , $ , e , $ , , . , < , , ,
, $ =
<
l % i = <
l % i = spin bus timing
if the psync function is enabled, this device will generate an internal sync signal to synchronize the received data in sdbr register, to indicate that the next receiving bit of data will be the msb. the following timing diagram illustrates the relationship between the sck and psync control signals in slave mode. note that if the spi is working under master mode, the psync function and the sync will be ignored by hardware. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 36 january 22, 2014 ) ! ) ! <
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dma function the HT82A525R provides both serial and parallel interface dma functions. the dma serial interface is implemented using one of the spi interfaces, either spi1 or spi2. the parallel dma is implemented using port d. dma overview for the serial dma interface, the spi1 related pins are pin shared with pe0~pe3, and the spi 2 related pins are pin shared with pc4~pc7. the parallel dma data lines are pin shared with port d, hsync is pin shared with pa4 and the pclk is pin shared with pa5. when the pdma bit in the clk register is set high, the parallel dma function will be selected and the data will be written to fifo2 directly. the fifo2 size is 64 3 bytes for parallel dma mode. fifo3 can t be use for parallel dma mode. psync/vsync is pin shared with the pa0 pin. vsync is used to synchronise the parallel dma data received data and psync is used to synchronise the serial dma received data. the sclk is pin shared with the pb0 pin and used as the clock output for serial or parallel dma functions. the clock output is controlled by the sclken and clkautob bits in the clk register. the clock output frequency, 12, 16, 24, 6, 8, 4, 3, 2 mhz is selected by the fsclk configuration option. bit no. label r/w function 0 sclken r/w sclk pin output control bit 0: disable; 1: enable 1 clkautob r/w sclk pin output halt control bit 0: when fifo3 is full or sclken is 0 ; 1: when sclken is 0 2 pdma r/w parallel dma function control bit 0: disable; 1: enable 3 pdata_sel r/w parallel dma data format select bit 0: receive odd parallel dma data only; 1: receive all parallel dma data 4 pdma_mod r/w parallel dma function select bit 0: fingerprint mode - for fingerprint application only 1: normal mode, for general purpose application 5 fig_pix r/w fingerprint frame pixel select bit 0: qvga mode (320 240); 1: cif mode (352288) this bit is used to select the fingerprint frame pixel if the pdma_mod is cleared to 0 . 6~7 undefined bit, read as 0 this control bit is used to control the sclk output no mater in serial or parallel dma mode. clk register rev. 1.60 37 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
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if the pdma bit is cleared to zero and the sdmaen bit in the misc register is set high, then the serial dma function will be enabled. the sbdr1 data of the spi1 or the sbdr2 data of the spi2, selected by the sdmsel bit in the misc register, will be written to fifo3. serial dma in the serial dma mode, the spi1 or spi2 data, selected by sdmasel bit, can be written to fifo3 directly. sclk is pin shared with the pb0 pin and used as the clock output for serial or parallel dma function. the clock output function is controlled by the sclken and clkautob bits in the clk register. the clock output frequency, (12, 16, 24, 6, 8, 4, 3, 2 mhz), is selected by the fsclk by configuration option. if the sben, sdmaen bits are set high, and pdma is cleared to zero, the spi interface dma will enter the master mode and start to send out the sck clock. if the spi is in the master mode and is used as a receiver, the sck clock will be stopped automatically when fifo3 is full and will restart again when fifo3 is not full. if the spi is in the slave mode and is used as a receiver, if fifo3 is full, the spi will stop receiving data. it will restart again if fifo3 is not full. the frequency of the sck is selected using the cks, m1 and m0 bits in the sbcr register. note that the sck clock output will stop at a low level if the cpol bit is set high and stop at a high level if the cpol bit is cleared to zero. each spi interface can support both master or slave mode dma. the direction of the spi dma is determined by the setio3 bit. the corresponding buffer size of 8, 16, 32 or 64 bytes is determined by bits dlen 0~1 by configuration option. parallel dma in the parallel dma mode, hsync is pin shared with pa4, pclk is pin shared with pa5 pin, the vsync is pin shared with pa0 pin and the parallel dma data d0~d7 pins are pin shared with pd0~pd7. hsync and the pclk are used to synchronize the data of the parallel interface pins which are pin shared with port d. sclk is pin shared with the pb0 pin and is used as the clock output for serial or parallel dma functions. the clock output function is controlled by the sclken and clkautob bits in the clk register. the clock output frequency of 12, 16, 24, 6, 8, 4, 3 or 2 mhz is selected by the fsclk configuration option. the parallel dma function can be used in fingerprint mode or normal mode, which is selected using the pdma_mod bit in the clk register. in the normal mode, the vsync signal of the parallel dma received data will be ignored. in the fingerprint mode, there are two frame pixel modes, the qvga mode (320x240 pixels) or the cif mode (352x288 pixels). they are selected by the fig_pix bit in the clk register. if the pdma bit is set high, the parallel dma data will be written to fifo2, the size of which is 64x3 bytes. there is only a slave mode for the parallel dma and the data length can be selected as 5 bits or 8 bits by configuration option. the fifo2 buffers will start receiving data when hsync is set high and stop receiving data when hsync is cleared to zero. if fifo2 is not full and hsync is cleared to zero to stop receiving data, then fifo2 should not receive any incoming data. only the received data in fifo2 can be delivered to the endpoint. not until the next hsync high signal can fifo2 start receiving data from the next buffer. if all buffers of the fifo2 are full before hsync has a falling edge, this received data should be ignored. there are two parallel dma data selections, to receive odd parallel dma data only or to receive all parallel dma data, selected by the pdata_sel bit in the clk register. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 38 january 22, 2014
if vsync is enabled, it can be used to synchronize the parallel dma data d0~d7. there are two types of vsync control signal. the following diagram illustrates the parallel dma interface control signals. symbol parameter min. max. unit pclk frequency 4 mhz pclk duty cycle 45 55 % t1 data setup time to pclk 5 ns t2 data hold time to pclk 7 ns t3 hsync to pclk delay 5 ns t4 horizontal blank time (t hblank ) 24 t pclk t5 vsync(tpye1) high pulse time 200 ns t6 vsync(tpye1) to hsync delay time 500 ns t7 vsync(tpye2) to hsync delay time 700 ns parallel dma data timing description rev. 1.60 39 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi 4 ) ! % % i , < = % % i , < = 9 8 3 / * ) ! < " = 6 9 7 ) ! < " / = 9 8 4 ) !
suspend wake-up or remote wake-up if there is no signal on the signal bus for over 3ms, the HT82A525R will go into suspend mode. the suspend line (bit 0 of the usc) will be set to 1 and a usb interrupt is triggered to indicate that the HT82A525R should jump to suspend state to meet the 500 a usb suspend current spec. in order to meet the 500 a suspend current, the firmware should disable the usb clock by clearing the usbcken (bit3 of the ucc) to 0 . the suspend current is about 300 a. the user can also further decrease the suspend current by setting the susp2 (bit4 of the ucc). but if the susp2 is set, user should make sure not to enable the lvr option, otherwise, the HT82A525R will be reset. if user set the susp2 (bit4 of the ucc) in the usb mode, user must set rctrl (bit7 of the ucc) before set susp2 (bit4 of the ucc), otherwise, usb will disconnected. when the resume signal is sent out by the host, the HT82A525R will wake-up the by usb interrupt and the resume line (bit 3 of the usc) is set. in order to make the HT82A525R work properly, the firmware must set the usbcken (bit 3 of the ucc) to 1 and clear the susp2 (bit4 of the ucc). if user set the rctrl (bit7 of the ucc) and susp2 (bit4 of the ucc) in the usb suspend, when it will wake-up user must clr rctrl (bit7 of the ucc) before clr susp2 (bit4 of the ucc). since the resume signal will be cleared before the idle signal is sent out by the host and the suspend line (bit 0 of the usc) is going to 0 . so when the mcu is detecting the suspend line (bit0 of usc), the resume line should be remembered and taken into consideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt is triggered. the following is the timing diagram: the device with remote wake-up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of the usc). once the usb host receive the wake-up signal from the HT82A525R, it will send a resume signal to the device. the timing is as follow: HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 40 january 22, 2014 ! . , # , - . l
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usb interface the HT82A525R has 4 endpoints (ep0~ep3). ep0~ep1 are support interrupt transfer, ep2~ep3 is support bulk transfer. there are 12 registers, including usc (20h), usr (21h), ucc (22h), awr (address+remote wake-up 23h), stall (24h), sies (25h), misc (26h), setio (27h), fifo0 (28h), fifo1 (29h), fifo2 (2ah) and fifo3 (2bh) used for the usb function. the fifo size of each fifo is 8 byte (fifo0), 8 byte (fifo1), 64 byte (fifo2) and 128 byte (fifo3), and total of 208 bytes. urd (bit7 of the usc) is usb reset signal control function definition bit. bit no. label r/w function 0 susp r usb suspend indication flag 0: not in suspend mode 1: in suspend mode when this bit is set to 1 (set by sie), it indicates that the usb bus enters the suspend mode. the usb interrupt is also triggered on any changes of this bit. 1 rmwk r/w usb remote wake-up command 0: disable 1: enable it is set by the mcu to force the usb host leaving the suspend mode. set rmwk bit to 1 to enable remote wake-up. when this bit is set to 1 ,a2 s delay for clearing this bit to 0 is needed to insure that the rmwk command is accepted by the sie. 2 urst r/w usb reset indication bit 0: no usb reset 1: usb reset this bit is set or cleared by usb sie. when the urst is set to 1 , this indicates that a usb reset has occurred and a usb interrupt will be initialized. 3 resume r usb resume indication bit 0: in suspend mode 1: resume when the usb leaves the suspend mode, this bit is set to 1 (set by sie). this bit will appear for 20ms, waiting for the mcu to detect it. when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, mcu should set the usbcken and susp2 (in the scc register) to enable the sie detect function. the resume will be cleared while the susp is set to 0 . when mcu detects the susp, the resume (which causes mcu to wake-up) should be remembered and token into consideration. 4 v33o r/w v33o enable control bit 0: turn off 1: turn on 5 pll r/w pll enable control bit 0: turn on 1: turn off 6 unused bit, read as 0 7 urd r/w usb reset signal control function definition 1: will reset the mcu 0: cannot reset the mcu usc (20h) definitions rev. 1.60 41 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed. the endpoint request flags (ep0if, ep1if, ep2if and ep3if) are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 , and then the usb interrupt takes place or not will depend on the endpoint 0~3 interrupt function via the configuration option. if the endpoint 0~3 interrupt function is configured as disable , then the usb interrupt will occur (if the usb interrupt is enabled, the corresponding interrupt is enabled and the stack is not full). if the endpoint 0~3 interrupt function is configured as enable , the usb interrupt will need to be managed by the endpoint interrupt control bits, eep0i~eep3i, in the usr register as well. the endpoint interrupt control bits are used to control which endpoint is accessed and generate interrupt. only when the related endpoint interrupt control bits are selected as enable , then the related usb interrupt will take place, otherwise, the usb interrupt will not occur. when the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 . bit no. label r/w function 0 ep0if r/w the endpoint 0 interrupt request flag 0: inactive 1: active when this bit is set to 1 (set by sie), it indicates that the endpoint 0 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 1 ep1if r/w the endpoint 1 interrupt request flag 0: inactive 1: active when this bit is set to 1 (set by sie), it indicates that the endpoint 1 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 2 ep2if r/w the endpoint 2 interrupt request flag 0: inactive 1: active when this bit is set to 1 (set by sie), it indicates that the endpoint 2 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 3 ep3if r/w the endpoint 3 interrupt request flag 0: inactive 1: active when this bit is set to 1 (set by sie), it indicates that the endpoint 3 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 4 eep0i r/w the endpoint 0 interrupt enable 0: enable 1: disable 5 eep1i r/w the endpoint 1 interrupt enable 0: enable 1: disable 6 eep2i r/w the endpoint 2 interrupt enable 0: enable 1: disable 7 eep3i r/w the endpoint 3 interrupt enable 0: enable 1: disable usr (21h) definitions HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 42 january 22, 2014
there is a system clock control register implemented to select the clock used in the mcu. this register consists of usb clock control bit (usbcken), second suspend mode control bit (susp2) and system clock selection (sysclk). if hirc oscillator is used and for usb mode should enable clk_adj bit for psd register to adjust system clock for temperature. the following table defines which endpoint fifo is selected, eps2, eps1 and eps0. bit no. label r/w function 0 1 2 eps0 eps1 eps2 r/w accessing endpoint fifo selection. eps2, eps1, eps0: 000: select endpoint 0 fifo 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: reserved for future expansion, cannot be used 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used if the selected endpoints do not exist, the related functions are not available. 3 usbcken r/w usb clock control bit 0: disable 1: enable 4 susp2 r/w suspend mode control bit 0: normal mode 1: halt mode this bit is used to reduce power consumption in suspend mode. in normal mode, clear this bit to 0 . in halt mode, set this bit to 1 to reduce power consumption. 5 unused bit, read as 0 6 sysclk r/w system clock oscillator frequency control bit 0: 12mhz 1: 6mhz this bit is used to specify the system clock oscillator frequency used by the mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 . if a 12mhz crystal oscillator or resonator is used, this bit should be cleared to 0 . 7 rctrl r/w 7.5k
resistor between usbdp and vbus select bit 0: without resistor 1: with resistor ucc (22h) definitions the awr register contains the current address and the remote wake-up function control bit. the ini - tial value of the awr is 000h 0. the address value extracted from the usb command is not to be loaded into this register until the setup stage is finished. bit no. label r/w function 0 wken r/w remote wake-up enable/disable 0: disable 1: enable 1~7 ad0~ad6 r/w usb device address awr (23h) definitions rev. 1.60 43 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
the stall register shows whether the corresponding endpoint works properly or not. as soon as the endpoint works improperly, the related bit in the stall has to be set to 1 . the stall will be cleared by the usb reset signal. bit no. label r/w function 0~3 stl0~ stl3 r/w stalled usb endpoints control 4~7 undefined bit, read as 0 stall (24h) definitions this bit is used to configure the usb sie to automatically change the device address with the value of the address+remote_wakeup register (42h). when this bit is set to 1 by f/w, the usb sie will update the device address with the value of the address+remote_wakeup register (42h) after the pc host has successfully read the data from the device by the in operation. the usb sie will clear the bit after updating the device address. otherwise, when this bit is cleared to 0, the usb sie will update the device address immediately after an address is written to the address+remote_wakeup register (42h). the sies register is used to indicate the present signal state which the usb sie received and also determines whether the usb sie has to change the device address automatically. bit no. label r/w function 0 adr_set r/w device address configuration bit 0: update device address immediately 1: update by the in operation 1 f0_err r/w accessed fifo0 errors indication bit 0: no errors 1: some errors this bit is set by the usb sie and cleared by f/w. 2~6 unused bit, read as 0 7 nmi r/w nak interrupt mask bit 0: not mask 1: mask sies function table HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 44 january 22, 2014
misc register combines a command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc will be cleared by usb reset signal. bit no. label r/w function 0 request r/w fifo request control bit 0: not requested; 1: requested after selecting the desired endpoint, fifo can be requested by setting this bit as high active. afterwards, this bit must be set low. 1 tx r/w the direction and transition end indication bit 0: read data from fifo; 1: write data to fifo this indicates the direction and transition end which the mcu accesses. when set as logic 1 , the mcu writes data to fifo. afterwards, this bit must be set to logic 0 before terminating request to indicate transition end. for reading action, this bit must be set to logic 0 to indicate that the mcu wants to read and must be set to logic 1 afterwards. 2 clear r/w clear requested fifo control bit 0: not clear; 1: clear this indicates an mcu clear requested fifo, even if the fifo is not ready. after clearing the fifo, usb interface will send force_tx_err to tell host that data under-run if host wants to read data. 3 sdmaen r/w serial dma control bit 0: disable; 1: enable this bit is used to control the enable or disable the sbdr of the serial interfaces (which is pin-shared with port e or port c) being written to fifo3 directly. spi interfaces can be controlled by mcu and mcu can transmit or receive data by writing or reading sbdr. it is allowed changing from 1 to 0 when the fifo is not full. 4 sdmasel r/w serial dma interface selection bit 0: serial interface 1 (pin-shared with port e) 1: serial interface 2 (pin-shared with port c) 5 setcmd r/w fifo command data indication bit 0: not setcmd token; 1: setcmd token 6 ready r fifo ready indication bit 0: not ready to work; 1: ready to work 7 len0 r/w host sent 0-sized packet indication bit 0: not 0-sized packet; 1: 0-sized packet misc (26h) definitions there are some timing constrains and usages illustrated here. by setting the misc register, mcu can perform reading, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writing and clearing. actions misc setting flow and status read fifo0 sequence 00h01h delay 2 s, check 41h read* from fifo0 register and check not ready (01h) 03h02h write fifo0 sequence 02h03h delay 2 s, check 43h write* to fifo0 register and check not ready (03h) 01h00h check whether fifo0 can be read or not 00h01h delay 2 s, check 41h (ready) or 01h (not ready)00h check whether fifo0 can be written or not 02h03h delay 2 s, check 43h (ready) or 03h (not ready)02h write 0-sized packet sequence to fifo0 02h03h delay 2 s, check 43h01h00h clear fifo0 sequence 01h delay 2s05h delay 2s00h note: *: there are 2 s existing between 2 reading action or between 2 writing action. read or write fifo table rev. 1.60 45 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
bit no. label r/w function 0 undefined bit, read as 0 1~3 setio1~3** r/w endpoints input or output pile selection bit 0: output pipe; 1: input pipe 4~7 undefined bit, read as 0 setio (27h) register, usb endpoint 1~endpoint3 set in/out pipe register note: *usb definition: when the host sends a set configuration , the data pipe should send the data0 (data toggle) first. so, when the device receives a set configuration setup command, user needs to toggle this bit so the next data will send a data0 first. **needs to set the data pipe as an input pile or output pile. the purpose of this function is to avoid the host from abnormally sending only an in or out token and disables the endpoint. label r/w function fifoi r/w epi accessing register (i = 0~3). when an endpoint is disabled, the corresponding accessing register should be disabled. fifo0~fifo3 (28h~2bh) register, usb endpoint accessing registers definitions bit no. label r/w function 0 ps2_dao r/w usbdm/data pin output control bit 0: output low ; 1: output high this control bit is used to generate the usbdm/data pin output signal in the 3d ps2 mouse mode. the default value is 1 . 1 ps2_cko r/w usbdp/clk pin output control bit 0: output low ; 1: output high this control bit is used to generate the usbdp/clk pin output signal in the 3d ps2 mouse mode. the default value is 1 . 2 undefined bit, read as unknown 3 pu r/w usbdp and usbdm internal 310k
pull-high resistor select bit 0: without pull up resistor; 1: with pull up resistor 4 clk_adj r/w automatic clock adjustment control bit 0: disable (default); 1:enable this bit is used to adjust the hirc mode system clock, to reduce the frequency deviation due to temperature issue. in the power-down mode, this bit should be clear to reduce power consumption. 5 clr_rcp r/w this bit is must enable and then disable by f/w to clear hirc initial parameters after power on. 0: disable (default); 1:enable 6~7 undefined bit, read as 0 psd (3ah) register HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 46 january 22, 2014 h 0 $ " > #

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pulse width modulator the device contains three pulse width modulation pwm outputs. useful for such applications such as motor speed control, the pwm function provides an output with a variable frequency, and with a duty cycle that can be varied by setting particular values into the corresponding register pair. channel pwm mode output pin register names 0 8+4 pa1 pwm0drl~ pwm0drh 1 8+4 pa2 pwm1drl~ pwm1drh 2 8+4 pa3 pwm2drl~ pwm2drh pwm registers three register, located in the data memory are assigned to each pulse width modulator output and are known as the pwm registers. it is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. the pwm registers also contain the enable/disable control bit for the pwm outputs. to increase the pwm modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. note that it is only necessary to write the required modulation value into the corresponding pwm register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. this method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is defined by register pwmbr and the system clock f sys or f sys /4 (chosen via the pwmn_s bit), and as the pwm value is 12-bits wide, the overall pwm cycle frequency ( f pwm )asthe following equation and the corresponding pwm modulation frequency for 8+4 mode is f pwm /256 . f pwm = 1 (1/ f )x(pwmbrn 1) sys + , when pwmn_s=0 f pwm = 1 (4 / f )x(pwmbrn 1) sys + , when pwmn_s=1 where pwmbrn=0~255 and f sys may be 6mhz, 12mhz , n=0~2 , according register whether it is pwm0, pwm1 or pwm2 pwm modulation frequency pwm cycle frequency pwm cycle duty f pwm /256 f pwm /4096 (pwm register value)/4096 rev. 1.60 47 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
8+4 pwm mode modulation each full pwm cycle, as it is 12-bits wide, has 4096 clock periods. however, in the 8+4 pwm mode, each pwm cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as i in the table. each one of these sixteen sub-cycles contains 256 clock cycles. in this mode, a modulation frequency increase of sixteen is achieved. the 12-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit4~bit11 is denoted here as the dc value. the second group which consists of bit0~bit3 is known as the ac value. in the 8+4 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~15) dc (duty cycle) modulation cycle i (i=0~15) i ac dc+1 256 i ac dc 256 8+4 mode modulation cycle values the accompanying diagram illustrates the waveforms associated with the 8+4 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 16 individual modulation cycles, numbered 0~15 and how the ac value is related to the pwm value. pwm output control the three outputs, pwm0, pwm1, and pwm2 are shared with pins pa1, pa2 and pa3. to operate as a pwm output and not as an i/o pin, bit 0 of the relevant pwm low byte register bit must be set high. a zero must also be written to the corresponding bit in the pac port control register, to ensure that the pwm0~2 output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm 12-bit value has been written into the pwm register pair register, setting the corresponding bit in the pa data register high will enable the pwm data to appear on the pin. writing a zero to the bit will disable the pwm output function and force the output low. in this way, the port a data output register bits, can also be used as an on/off control for the pwm function. note that if the enable bit in the pwm register is set high to enable the pwm function, but if the corresponding bit in the pac control register is high to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 48 january 22, 2014
pwm programming example the following sample program shows how the output is setup and controlled. mov a,64h ; setup pwm0 value to 1600 decimal which is 640h mov pwm0h,a ; setup pwm0h register value clr pwm0l ; setup pwm0l register value clr pac.1 ; setup pin pa1 as an output set pwm0en ; set the pwm0 enable bit set pa.1 ; enable the pwm0 output :: :: clr pa.1 ; pwm0 output disabled pa1 will remain low bit r/w description 7~0 r/w used to define the base period of the pwm range =1 ~ 256 (1/f sys or 4/f sys chosen via the pwmn_s bit) where pwmbrn=0~255 (n= 0~2) pwm base period register pwmbr0 ~ pwmbr2 rev. 1.60 49 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi ( )
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com function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, com0~com3, are pin shared with certain pin on the pd0~ pd3 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pd0~pd3 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the lcdc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary vddio/2 voltage levels for lcd 1/2 bias operation. the lcden bit in the lcdc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port d pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. if the parallel dma function is disabled, pdma control bit is set to 0 , and the comnen bits is set to 1 will enable the corresponding lcd com driving waveform to port d pins. lcden comnen pin function o/p level 0 x i/o 0or1 1 0 i/o 0or1 1 1 comn v ddio /2 output control HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 50 january 22, 2014
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lcd bias control the lcd com driver enables two kinds of selection to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the rsel0 and rsel1 bits in the lcdc register. bit no. label r/w function 0 com0en r/w pd0 or com0 selection 0: gpio 1: com3 1 com1en r/w pd1 or com1 selection 0: gpio 1: com3 2 com2en r/w pd2 or com2 selection 0: gpio 1: com3 3 com3en r/w pd3 or com3 selection 0: gpio 1: com3 4 lcden r/w com module control 0: disable 1: enable 5 6 rsel0 rsel1 r/w select scom typical bias current (v dd =5v) 00: 25 a 01: 50 a 10: 100 a 11: 200 a 7 r/w reserved bit 0: correct level, bit must be reset to zero for correct operation 1: unpredictable operation, bit must not be set high lcdc register (3bh) rev. 1.60 51 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
options the following table shows all kinds of otp option in the microcontroller. all of the otp options must be defined to ensure proper system functioning. the default values of the options are 0 . no. option i/o options 1 pa0~pa7 wake-up function: enable or disable -- bit option 2 pa0~pa7 pull-high resistor function: enable or disable -- bit option 3 pb0~pb7 pull-high resistor function: enable or disable -- bit option 4 pb0~pb7 wake-up function: enable or disable -- nibble option 5 pb0~pb7 output structure option: cmos or nmos -- bit option 6 pc0~pc7 pull-high resistor option: enable or disable -- nibble option 7 pc0~pc7 wake-up function: enable or disable -- nibble option 8 pd0~pd7 pull-high resistor function: enable or disable -- nibble option 9 pd0~pd7 wake-up function: enable or disable -- nibble option 10 pe0~pe7 pull-high resistor function: enable or disable -- nibble option 11 pe0~pe7 wake-up function: enable or disable -- nibble option 12 pf0~pf1 pull-high resistor function: enable or disable -- nibble option 13 pf0~pf1 wake-up function: enable or disable -- nibble option oscillator option 14 osc, osc mode selection: external crystal or internal rc osc spi options 15 sclk function: enable or disable 16 fsclk; sclk frequency selection: 12mhz, 16mhz, 24mhz, 6mhz, 8mhz, 4mhz, 3mhz, 2mhz 17 spi1 function: enable or disable 18 spi1 wcol function: enable or disable 19 spi1 csen function: enable or disable 20 spi1 clock polarity selection: rising or falling edge 21 spi1 data output mode option 22 spi2 data output mode option 23 pclk function: enable or disable 24 spi2 function: enable or disable 25 spi2 wcol function: enable or disable 26 spi2 csen function: enable or disable 27 spi2 clock polarity selection: rising or falling edge HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 52 january 22, 2014
no. option dma options 28 psync/vsync function: enable or disable 29 parallel dma data length option: 8bit or 5bit 30 dlen;spi dma fifo output data length option: 64 bytes, 32 bytes, 16 bytes, 8 bytes 31 hsync function: enable or disable 32 pclke clock polarity option: rising or falling edge wdt options 33 wdt function: enable or disable 34 wdt clock source option: f sys /4 or wdtosc 35 wdt timeout period option: 2 13 /f s ,2 14 /f s ,2 15 /f s ,2 16 /f s 36 timer out wdt clear mode option: half wdt clear or full wdt clear usb options 37 ep1, ep2, ep3 data pipe function: enable or disable 38 endpoint 0~3 interrupt function: enable or disable lvr option 39 lvr enable or disable other options 40 tbhp enable or disable 41 vsel; lcd com voltage option (ice only): 3.3v or 5.0v application circuits note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that vdd is stable and remains within a valid operating voltage range before bringing res high. x1 can use 6mhz or 12mhz, x1 as close osci & osco as possible. * these capacitors should be placed close to the usb connector. ** this capacitor should be placed close to the mcu. rev. 1.60 53 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi 8 9 . 8 . 9 8 9 . . 3 3 0 6 ? . 2 . 1 3 3 3 3 0 0 j 4

0 ? j 0 j j ? 8 9 8 9
instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be implemented within 1 s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 54 january 22, 2014
examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.60 55 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 56 january 22, 2014
mnemonic description cycles flag affected bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] (4) tabrdc [m] (5) tabrdl [m] read rom code (locate by tblp and tbhp) to data memory and tblh read rom code (current page) to data memory and tblh read table (last page) to tblh and data memory 2 note 2 note 2 note none none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. 4. configuration option tbhp option is enabled 5. configuration option tbhp option is disabled rev. 1.60 57 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 58 january 22, 2014
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cy - cle instruction. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con- junction with clr wdt2 and must be executed alternately with clr wdt2 to have ef- fect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con - junction with clr wdt1 and must be executed alternately with clr wdt1 to have ef - fect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf rev. 1.60 59 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain un - changed. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the con - tents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 60 january 22, 2014
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z rev. 1.60 61 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pend- ing when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data mem - ory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 62 january 22, 2014
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 re - places the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c rev. 1.60 63 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec- ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 64 january 22, 2014
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec - ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruc- tion. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the re- sult is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the re - sult is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is neg - ative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c rev. 1.60 65 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain un - changed. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following in - struction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 66 january 22, 2014
tabrdc [m] move the rom code (locate by tblp and tbhp) to tblh and data memory (rom code tbhp is enabled) description the low byte of rom code addressed by the table pointers (tblp and tbhp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z rev. 1.60 67 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. further package information (include outline dimensions, product tape and reel specifications) packing meterials information carton information HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 68 january 22, 2014
24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.341 bsc d 0.069 e 0.025 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 08 symbol dimensions in mm min. nom. max. a 6.0 bsc b 3.9 bsc c 0.20 0.30 c 8.66 bsc d 1.75 e 0.635 bsc f 0.10 0.25 g 0.41 1.27 h 0.10 0.25 08 rev. 1.60 69 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi / * 3 / . n ( 4
saw type 32-pin (5mm 5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.007 0.010 0.012 d 0.193 0.197 0.201 e 0.193 0.197 0.201 e 0.020 bsc d2 0.122 0.126 0.130 e2 0.122 0.126 0.130 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.700 0.750 0.800 a1 0.000 0.020 0.050 a3 0.203 bsc b 0.180 0.250 0.300 d 4.900 5.000 5.100 e 4.900 5.000 5.100 e 0.500 bsc d2 3.100 3.200 3.30 e2 3.00 3.200 3.30 l 0.35 0.40 0.45 k 0.20 HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 70 january 22, 2014 d 3 / % / ; : 7 9 / * / 6 3 /
48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.276 bsc c 0.354 bsc d 0.276 bsc e 0.020 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.063 i 0.002 0.006 j 0.018 0.024 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0.50 bsc f 0.17 0.22 0.27 g 1.35 1.40 1.45 h 1.60 i 0.05 0.15 j 0.45 0.60 0.75 k 0.09 0.20 07 rev. 1.60 71 january 22, 2014 HT82A525R i/o type usb 8-bit otp mcu with spi 3 7 / 6 3 9 / * 3 / * ; . ( 4
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HT82A525R i/o type usb 8-bit otp mcu with spi rev. 1.60 72 january 22, 2014 copyright 2014 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publica - tion. however, holtek assumes no responsibility arising from the use of the specifications de - scribed. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without fur - ther modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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